CMOS Receiver and mm-Wave Front-End Components for Integrated High-Speed Communication Systems

Recent advances of the ongoing project phases of the projects PolyData and DataRate are shown. The first involves the 3D-integration of a small transmitter array and a CMOS power amplifier at W-band using a low-cost stereolithographic process. The available bandwidth of 35GHz, dual-polarization, and the use of moderately complex modulation schemes suffice there for data rates up to 100Gbit/s. The latter project is to extend this concept to a complete receiver with independent beam steering for the two polarizations and to demonstrate data transmission at 100Gbit/s. An advanced front-end consisting of a wideband, circularly polarized antenna at W-band and its subsequent receiver chip for 100Gbit/s will be implemented in a system-in-package and will be used as an element of a larger array. The chip, realized in 22nm FDSOI CMOS, shall include RF to IF down-conversion and conversion to the digital domain. Therefor it is comprised of a low-noise amplifier, a resistive mixer with enhanced LO-RF isolation, a distributed amplifier, a truly balanced push-push frequency quadrupler and a baseband ADC operating at 74GS/s. In particular challenges on non-idealities as well as area efficient design and minimizing power consumption are discussed comparing different ADC topologies.