A DC–50GHz DPDT Switch with >27dBm IP1dB in 45nm CMOS SOI

This paper presents a DPDT T/R switch in a 45nm CMOS SOI process. The switch employs shunt-series-shunt topology with thin-oxide transistor having low on-resistance in the series branch to provide low insertion loss and thick-oxide transistor having higher threshold and breakdown voltage in the shunt branch to offer high linearity. Together with resistive stacking of transistors and negative biasing schemes for further linearity and isolation enhancement, the proposed design achieves broadband operation from DC to 50GHz, with <3dB IL, >22dB isolation with power handling capability greater than half a watt.