Recently, increased efforts have been directed towards building quantum processors using Josephson junction structures. This approach mandates a separate classic electronic control IC which brings a bottleneck in I/O connections to the quantum die, limiting the maximum number of qubits that can be implemented to few tens. Silicon based spin-qubits have been proposed as a solution to scaling the quantum processor to higher qubit counts. However, the high-power dissipation per qubit in the RF control circuits needed to manipulate the electron spin places a hard thermal limitation to few hundred qubits for the processor. Practical scalable quantum processors need to have qubit counts in many thousands to one million and beyond. Such architecture requires a very low power control circuit which can be achieved only through single-chip integration with low interconnect parasitics. This presentation describes a monolithic integration of the semiconductor quantum core and its associated classic electronic control and read-out circuitry in a 3×3mm² 22nm FD-SOI SoC die containing 28 quantum experiment cells. Thanks to the low transistor leakage in cryogenic environment, a switch capacitor topology is used extensively in designing the control and read-out circuits. The resulting thermal budget from active and passive loads is a fraction of the cooling power and thus the solution can be scaled to a large number of qubits.