Recent Trends in Low-Power Low-Jitter Digital Phase-Locked Loops

One of the key challenges in wireless transceivers is to reduce the power consumption of phase-locked loops (PLLs) while satisfying their requirements on phase noise (PN), spurious tones, and settling times. To fully benefit from the scaling of CMOS technology, all-digital PLLs (ADPLL) appear more promising than their traditional analog counterparts as they also allow seamless digitally intensive calibrations. This talk will cover fundamental of time-domain all-digital phase-locked loop (ADPLL), power versus jitter tradeoff in high-performance PLL/ADPLLs design, and recent techniques in high-performance PLL/ADPLLs such as digital-to-time(DTC)-assisted approach, subsampling/sampling and oversampling digital architectures for various applications.