Characterizing and Modeling of Safe Operating Area for SiGe NPNs in Tower’s SBC18 Technology
The demand for silicon-based PA technology has grown with the rapid growth of popular wireless applications such as 5G, WiFi, NFC, GPS, IoT and Bluetooth, coupled with the emergence of other analog markets such as smart energy and automotive. One of the key benefits of SiGe HBTs over CMOS is the ability to operate at higher voltages, necessitating careful and comprehensive characterization and modeling of the Safe Operating Area (SOA) in a HBT so robust ICs can be designed. The SOA of an HBT is typically limited by four phenomena: 1) Self/Mutual-heating where localized temperature increase due to power dissipation in the SiGe NPN can lead to thermal runaway and irreversible device degradation and/or destruction, 2) Avalanche breakdown at high Vce that is dependent on the base impedance and temperature, 3) Beta degradation, which is a long-term reliability limit and manifests itself as a reduction in current gain (Beta) of the SiGe NPN due to an increase in the non-ideal (low Vbe) base current, and 4) the EM (Electromigration) limit of the interconnect leading into the SiGe NPN. In this tutorial, the characterization, modeling and PDK implementation of the above SiGe NPN SOA phenomenon will be presented with a goal of providing foundry validated and easy to use design verification tools for BiCMOS design teams that minimize the dependence on manual load-line based techniques that may have been traditionally used, and at the same time enabling rapid iteration between design and verification. A SiGe BiCMOS RF IC design will be used to highlight key features of this verification flow. Finally, future needs and enhancements will be discussed.