Architecting Wireline Transceivers for Beyond 1Tbps Applications

Modern wireline transceivers have transitioned from predominantly RF/analog/mixed-signal designs to sophisticated digital modems comprising analog front-ends, data converters, and a large custom DSP. CMOS technology scaling favors the trend toward DSP-based architectures. Subtle interactions that arise between the analog front-end and digital equalization, timing recovery, and forward error correction can impact BER, and thus transceiver design, significantly. This talk will elucidate these interactions, highlighting critical considerations in the design of 224Gbps transceivers for 1.6T applications and beyond.