Back-gate lumped resistance effect on AC characteristics of FD-SOI MOSFET

In this work, the impact of a large lumped resistor connected to the back-gate of an FD-SOI transistor is studied. A related transition in the frequency responses of output conductance and capacitance is evidenced experimentally by S-parameters measurements in a large frequency range up to 40 GHz. However, present compact model does not correctly reproduce the back-gate/substrate network behaviour. This calls for a model accounting for both n-well and substrate networks. A small-signal equivalent circuit including distributed elements is thus proposed and compared with experimental results.