Nonlinear Analysis of Oscillators Based on a Slow-Wave Structure for Phase-Noise Reduction

An in-depth investigation of oscillators containing a slow-wave structure for phase-noise reduction is presented. The analysis is carried out by extracting a nonlinear admittance function from a harmonic-balance simulator, which is combined with the passive linear admittance of the delay network. As will be shown, a sequence of distinct oscillation curves is obtained when varying the time delay, which are generated and extinguished at Hopf bifurcations. The formulation provides insight into this complex pattern, resulting from the strong impact of the delay-network parameters on the steady-state oscillation. The mechanism for phase-noise reduction is understood with the aid of an analytical expression that enables an estimation of the delay required for a given phase-noise improvement. The methods have been successfully applied to a FET-based oscillator at 2.3 GHz.