A 0.013-mm² 40–67-GHz Voltage-Controlled Distributed Attenuator with 1.9-dB Insertion Loss and Sub-6.1° Insertion Phase Imbalance

This paper presents a V-band voltage-controlled distributed attenuator in a 65-nm CMOS process. This attenuator combines a distributed attenuation unit with two simplified T-type switched attenuators to expand the attenuation range while reducing its insertion loss. A phase compensation block is applied to reduce the phase imbalance and a stacked transmission line is proposed to minimize the chip area while improving the insertion loss performance. With a compact area of 0.013 mm², the proposed attenuator achieves an attenuation range of 15 dB with an insertion loss of 1.9–2.6 dB over 40–67 GHz. Across all attenuation states, the phase imbalance is less than 6.1° relative to the reference state. Compared with the state-of-the-art results, the proposed attenuator achieves the highest ratio of the attenuation range over the chip area.