Package-to-Package Scale-Out Interconnect Solutions Based on In-Package Optical I/O

Next generation compute hardware, especially for generative AI applications — but also for coming 5G/6G massive MIMO and scalable phased array antenna beamforming and other applications — requires massive scale-out of compute, while maintaining performance, that is possible only with high bandwidth, high bandwidth density, low latency, low energy, and low cost per bit optical interconnects. I will describe the industry’s first optical I/O chiplet technology that will enable this transformation, based on Ayar Labs TeraPHY silicon photonic I/O chiplets and SuperNova multi-wavelength, multi-port light sources. The technology enables 100+Tbps per package scale optical I/O at few pJ/bit energies in a commercially manufactured technology. The technology is based on silicon CMOS I/O chiplets with silicon waveguides and micro-ring resonators as optical modulators, filters and photodetectors, monolithically integrated with state-of-the-art RF-CMOS electronics in a single SoC, and separate light source devices. I will describe some of the history of the development of this technology as an essential element of the new chiplet paradigm for computing, its current status and roadmap. I will also briefly highlight a few future looking projects that are university collaborations enabled by the same platform, such as analog photonic links for RF/mm-wave MIMO beamforming, links for superconducting compute, and quantum transceivers.