Cryogenic CMOS Architectures for Large-Scale Quantum Computers

A fault-tolerant quantum computer operates at deep cryogenic temperatures (typically <100mK) and requires thousands of quantum bits (qubits) for running practical quantum algorithms. CMOS integrated circuits operating at cryogenic temperatures down to 4K (Cryo-CMOS) can offer significantly higher system integration and guarantee scalability for future quantum computers. However, Cryo-CMOS circuits must satisfy extremely demanding noise and linearity requirements for quantum-processor control and readout at a minimal power budget. In this presentation, we first focus on a digitally-intensive wideband transmitter that can potentially control 32 frequency-multiplexed qubits, simultaneously. It also offers waveform shaping flexibility, minimum execution latency, and straightforward integration in the existing quantum computing stack. The results of a Rabi experiment on a sample with one single-electron silicon spin qubit are also shown to demonstrate the capability of the transmitter in controlling qubits. Then, we switch the gears to the challenges of low-noise signal amplification in the qubit readout chain. We exploit the reduced loss of passive components at cryogenic temperatures to realize a phase-insensitive parametric amplifier. Finally, we talk about the frequency generation at cryogenic temperatures and reveal a new phase-locked loop architecture with extremely low jitter.