Sub-6GHz SOI-CMOS High-Efficiency Linear PA Architectures: Challenges, Techniques, and Opportunities

High peak-to-average power ratio (PAPR) signals used in LTE and 5G systems require the power amplifier (PA) to be backed-off from its peak power in order to achieve the necessary system linearity. Linear amplification of high PAPR signals is traditionally achieved by PA operating in back-off where conventional linear PA architectures show poor efficiency. The Doherty PA architecture, that relies on load modulation to improve efficiency in back-off, represents an attractive solution for efficient amplification of high PAPR signals. In this talk, high-efficiency linear SOI-CMOS Doherty PA designed to operate in sub-6GHz bands will be described and recent measurement results will be presented.